The present invention relates to a semiconductor memory device and, more particularly, to an internal power supply circuit for generating an internal power supply voltage in a DRAM.
Recently in the field of semiconductor memories represented by the DRAM, the memory capacity increases, and transistors integrated on a chip are miniaturized.
Since the electrical breakdown voltage of a small transistor is low, an external power supply voltage VCC is stepped down by an internal power supply voltage generation circuit arranged on the chip to generate an internal power supply voltage VINT, and the internal power supply voltage VINT drives an integrated circuit formed on the chip.
A conventional internal power supply voltage generation circuit is constituted by a large-size N-channel MOSFET (NMOS). That is, the external power supply voltage VCC is supplied to the drain of this NMOS to obtain the internal power supply voltage VINT from its source.
A voltage generation circuit of this type can advantageously increase a load current. Even when a DRAM chip becomes active, and the integrated circuit formed on the chip consumes a large amount of internal power supply voltage VINT, a sufficient internal power supply voltage VINT can be supplied in accordance with the consumption.
The voltage generation circuit using an NMOS can advantageously increase a load current, but the load current is difficult to decrease. That is, even when the DRAM chip changes to a standby state, and the internal integrated circuit hardly consumes the internal power supply voltage VINT, the NMOS of the voltage generation circuit continuously flows a current from the external power supply VCC to the internal power supply VINT.
In the DRAM on which this voltage generation circuit is mounted, the consumption amount of external power supply voltage VCC is difficult to reduce, which makes it difficult to further reduce power consumption.
The consumption amount of external power supply voltage VCC can be reduced by turning "off" the NMOS of the voltage generation circuit when the chip changes to, e.g., a standby state.
However, the NMOS of the voltage generation circuit has a large size, charging/discharging the gate requires a long time, and the NMOS cannot be turned "on/off" at high speeds. In practice, of semiconductor memory devices, a DRAM, particularly a synchronous DRAM demanded for high-speed operation is always kept "on" regardless of the active/standby state of the chip.